Department of Microelectronics CVUT and its Electron
Device Group (EDG) has more than 30 year experience in the field of
characterization of power devices and materials, lifetime and defects
engineering, development of application-specific diagnostic methods, and
calibration of simulation models including the effect of structural
defects. Main contribution of CVUT to the SPEED project is a scientific
expertise in the characterization of SiC material, epilayers, and device
structures for voltages higher than 3kV. This includes electrical and
optical characterization of SiC material and structures including
development of specific diagnostic tools, development of methods for
lifetime control in SiC epilayers and bipolar structures, calibration of
appropriate simulation models and verification of device concepts. CVUT
disposes several labs with research facilities for comprehensive
diagnostics of electrical and optical properties of defects in
semiconductors and their influence on device characteristics. Its
laboratories allow complete electrical characterization of investigated
SiC structures and advance defect diagnostics using DLTS, PL, FIR, AFM,
etc. The diagnostics is supported by use of device simulation (SILVACO,
Inc.).
CVUT participates to two work packages (WP) in the
framework of the SPEED project: WP 1 (Advanced SiC Materials: Substrates
and Epi) and WP3 (High-Voltage SiC Device & Packaging Technologies for
Power Transmission Applications).
Within the WP1, CVUT participates together with
ASCATRON, NORSTEL, FhG IISB, INAEL on Task 1.3 SiC Epitaxy for Bipolar
Devices. This task focuses on the growth of n-type SiC layers with the
desired properties (thick and low-doped layers with long carrier
lifetime) and the growth of a highly doped p-anode layers on the top of
them. The epilayer growth is performed by Ascatron and Norstel. CVUT
participates namely in Sub-task 1.3.2. “Carrier lifetime enhancement
technology”. This part of the project focuses on the increase of the
carrier lifetime from current 2-3μsec to more than 10μsec. This is
necessary for realization of efficient carrier injection and enabling
conductivity modulation in bipolar devices. The lifetime killers in SiC
are namely defects involving carbon vacancies, but also other defects,
e.g., atoms of contaminants can play an important role. The carrier
lifetime can be increased by proper control of epilayer growth, reducing
the number of carbon vacancies employing process steps like high
temperature thermal oxidation and/or carbon implantation with subsequent
high temperature annealing. CVUT supports the development by its
expertise in defect diagnostics (DLTS), electrical characterization
(lifetime measurement) and device simulation. CVUT is also taking part
in the Sub-task 1.3.4. “Production process of epitaxial material for
very high voltage devices” which focuses on production of friendly
process to cost effective manufacture the epitaxial wafer material for
high voltage SiC devices. Again, CVUT provides the feedback to epitaxial
wafer producer providing the analysis of material properties of produced
wafers.